1. Field of the Invention
The present invention relates to an output buffer circuit and, in particular, to an output buffer circuit which can improve noise and output speed of data by adjusting a preset signal generated from a preset signal generation circuit.
2. Background of the Invention
In general, a preset type output buffer consists of an output driver circuit and a preset signal generation circuit. The output driver circuit has preset pull up and pull down transistors and main pull up and pull down transistors. The preset pull up and pull down transistors are driven by the preset signal generation circuit. In the output buffer having such structure, after a potential of an output node is precharged to some degree by turning on of the preset pull up and pull down transistors, the main pull up and pull down transistors are driven so that a resultant data is output through an output terminal.
A conventional preset signal generation circuit will be described below with reference to FIGS. 1a and 1b.
FIGS. 1a and 1b are timing diagrams of a conventional output buffer and a preset signal generation circuit of the output buffer, respectively, however, only the timing diagrams of pull down procedure is shown.
As shown in FIG. 1a, if an address ADD is changed at t1 time point to read data stored in a memory cell, an address transition detector ATD generates an ATD pulse having high state. The address transition detector ATD is used for detecting the address at the time of read operation of memory cell, and the read speed of data can be improved and the power consumption can be reduced by using the ATD pulse generated by the address transition detector ATD. At this time, the preset signal PRESET generated by the preset signal generation circuit becomes high state so that the preset pull up or pull down transistor is turned on according to the state of previously sensed data so as to precharge the potential of the output node and then turned off. Thereafter, the main pull up and pull down transistors are turned on according to a main pull up and down transistor drive signal MAIN so that the resultant data is output through the output terminal.
A procedure of generating the preset signal will be described with reference to FIG. 1b.
A preset enable signal OPB is generated by using the ATD pulse, has a pulse width same as that of ATD pulse, and becomes high state at the time of driving the preset signal generation circuit. An input signal SOUTb is an inversed data of previously sensed data.
First, the operation of the preset signal generation circuit in case where the level of the previously sensed data is high will be described. At this time, since the input signal SOUTb becomes low state, the output signal of a NOR gate G1 becomes low state. Accordingly, a first PMOS transistor P1 is turned on while a first NMOS transistor N1 is turned off so that a source voltage is supplied through the first PMOS transistor P1 and finally an output signal pup becomes high state. On the other hand, since an output of a NAND gate G2 also becomes low state, a second PMOS transistor P2 is turned on while a second NMOS transistor N2 is turned off so that the source voltage Vcc is supplied through the second PMOS transistor P2 and finally an output signal pdp becomes high state.
In case where the previously sensed data is low state, the input signal SOUTb becomes high state and the output of the NOR gate G1 becomes high state. Accordingly, the first PMOS transistor P1 is turned off while the first NMOS transistor N1 is turned on so that an electric current pass occurs to a ground terminal Vss. Finally the output signal pup becomes low state. In addition, the output of the NAND gate G2 becomes high state, whereby the second PMOS transistor P2 is turned off while the second NMOS transistor N2 is turned on so that an electric current pass occurs to the ground terminal Vss. Finally the output signal becomes low state.
Thereafter, the output signals pup and pdp of such preset signal generation circuit is input to an output driver. Then the preset enable signal OPB becomes low state so that the preset signal generation circuit is disabled, and at this time of t2 in FIG. 1a, the main pull up and pull down transistor drive signal MAIN becomes high state so that the resultant data is output.
In case of the output buffer using such preset signal generation circuit, the preset signal generation circuit is disabled before the main pull up and pull down procedure is performed, and this has problems in that the electric current flows discontinuously at this time, a noise occurs accordingly and the data output speed is decreased.